The present invention relates to anneal or thermal treatment, and/or surface passivation of semiconductor alloys of the formula Hg(1−x)Cd(x)Te wherein the x-value is between 0.1 and 0.5, generically referred to as “HgCdTe”, which includes HgCdTe grown on lattice constant matched CdZnTe substrates and lattice constant and coefficient of thermal expansion (CTE) mismatched substrates such as Si. HgCdTe is a versatile infrared detector material whose bandgap can be varied by adjusting the x-value. For instance, x=0.2 corresponds to bandgap of ˜0.1 eV for LWIR (long wavelength infrared) detection, x=0.3 corresponds to ˜0.25 eV for MWIR (mid-wavelength infrared) detection and x=0.4 to 0.5 for SWIR (short wavelength infrared). The as-grown epitaxial HgCdTe materials have high density of defects such as dislocations due to the mismatched lattice constants and coefficient of thermal expansion (CTE), especially those epitaxially grown on Si substrate. Other defects such as metal vacancies, low, and Te-precipitates or inclusions, and interface fixed charge may also be present. Also there are extrinsic dopants such as arsenic and indium that needs to be activated to become electrically active. For eliminating the defects and activating the dopants, the HgCdTe materials are annealed or heat treated at various stages of material and device processing. These anneals or thermal treatments are mostly under Hg-rich condition provided by sealing the HgCdTe with a small amount of pure Hg in a fused quartz ampoule as depicted in FIG. 1. At 250 C anneal temperature the pure Hg provides a substantial vapor (0.3 atm), as can be seen in FIG. 2. Without the Hg-rich environment, a large concentration of Group II (metal) vacancy, which is a point defect, p-type dopant and S-R (Shockley-Reed) recombination center, can be generated, by loss of Hg from lattice sites to the atmosphere or Hg sinks. The equilibrium vacancy concentration has been determined and can be found in the literature. For instance, the vacancy concentration in HgCdTe (x˜0.21) at 250 C is 2E15 cm-2 when anneal is done without the addition of Hg. At another popular anneal temperature of 370 C, the Hg partial pressure is 1.3 atm; which containment poses a challenge for manufacturing as a pressurized vessel is needed. Other HgCdTe anneals are also done under pressurized conditions in sealed ampoules. For example, U.S. Pat. No. 4,481,044 (1984) entitled “High-temperature Hg anneal for HgCdTe,” Schaake, et al. used a Hg-anneal method to reduces the concentration of metal vacancies, prevents formation of dislocation loops or dislocation multiplication, as well as reduces tellurium precipitates which contribute to dislocation multiplication during subsequent post anneal. For another example, in U.S. Pat. No. 5,079,192 (1992) entitled “Method of preventing dislocation multiplication of bulk HgCdTe and LPE films during low temperature anneal in Hg vapor,” Tregilgas, et al. disclosed a method of forming samples of alloys of group II-VI compositions having minimum dislocations, comprising the steps sealing a HgCdTe sample in an enclosed ampoule having the sample at one end portion thereof and a group II element of the compound at an end portion remote from the one end portion, heating the sample to a temperature in the range of 350 C while maintaining the group II element at a temperature more than 200 C. Also Farrell, et al. employed thermal cycle anneal (TCA) of MBE grown HgCdTe/Si Layers at ˜400-500 C for dislocation reduction, Journal of Electronic Materials, Vol. 39, No. 1, page 43, 2010, where the anneal was also done in Hg-rich environment in sealed quartz ampoule. For passivation of HgCdTe surfaces, US 2003-0000454 A1 described using both Cd and Hg simultaneously at between 250 C and 400 C for annealing HgCdTe double layer or multilayer mesa photodiode structures in sealed quartz ampoules.
There have been attempts to anneal HgCdTe under Cd-rich condition. Wan, et al. suggested in U.S. Pat. No. 5,599,733 (1997), “Method using cadmium-rich CdTe for lowering the metal vacancy concentrations of HgCdTe surfaces” wherein HgCdTe was also coated with Cd and CdTe mixture and annealed at 250 C for annihilating the Hg vacancies. Cockrum et al. suggested in U.S. Pat. No. 5,880,510 a method of using a passivation layer by diffusing Cd on a junction interface of an HgCdTe junction diode, thereby increasing Cd composition ratio. According to the '510 patent, Cd or CdTe is thermally deposited on a junction interface of a HgCdTe junction diode and then annealed at 400 C. for 4 hours under a saturated Hg atmosphere. Cd from Cd or CdTe deposited by this process is diffused onto HgCdTe and Hg is diffused out of the HgCdTe, which raises the Cd composition ratio at the surface regions of HgCdTe. This is followed by annealing at 250 C. for 4 hours under a saturated Hg atmosphere in order to fill Hg voids generated in the crystal lattice of HgCdTe so that electrical characteristic can be controlled. Cockrum et al. teach that due to the high Cd composition ratio in surface regions of HgCdTe, electrons and holes are reflected therefrom and are prevented from rejoining together at the surface regions. The CdTe/Cd films were conductive due to the presence of Cd; they had to be removed by polishing for preventing surface shunting.
Suh, Sang-Hee et al. suggested a method for “Passivation of HgCdTe junction diode by annealing in Cd/Hg atmosphere” by forming a HgCdTe passivation layer with high Cd composition ratio on a HgCdTe semiconductor made of Group II-VI materials. They suggested annealing the HgCdTe in an anneal ampoule with both Cd and Hg sealed therein. The passivation layer was formed due to the Cd vapor generated by Cd while Hg vacancies were filled by the Hg vapor generated in the anneal ampoule. Thus deposition of CdTe film can be ignored for simplification. However, annealing the HgCdTe in a fused quartz ampoule with Cd vapor is impractical because the partial vapor pressure of Cd at 250 C are too low (˜1/10,000) and gas phase diffusion coefficient, being inversely proportional to the square root of the total pressure, is too low as well, which make the transport of the Cd source from source end of the ampoule to the HgCdTe substrate/wafer end difficult.
There were reports of using Cd for enhancing arsenic doping efficiency during growth of CdTe buffer layer by MBE. The crystallinity of CdTe buffer layers grown at 300 C was improved when the Cd/Te flux ratio was 1.8 (K. Maruyama, et. al. Journal of Crystal Growth Volume 137, Issues 3-4, 1 Apr. 1994, Pages 435-441). The purpose of using Cd flux was for growing CdTe buffer layer, not for annealing HgCdTe.
Surface passivation for getting rid of surface (interface) fixed charge and/or interfacial defect is an important aspect for the fabrication of HDVIP (High Density Vertically Integrated Photodetectors). A complex process called double-side interdiffusion (DSID) as described in U.S. Pat. No. 5,846,850 of Dreiske, et al., has been used for passivation of both front and back side of the HgCdTe on a CTE matched CdZnTe “sacrificial substrate” for avoiding dislocations generated by using CTE-mismatched Si substrate albeit the latter is much cheaper. The “sacrificial substrate” process is tedious and difficult to control; an alternate process that allows the 250 C passivation anneal to be performed after the bonding without damaging the HgCdTe is simpler and much easier to control.
Fabrication process of bump-bonded HgCdTe focal plane array (FPA) is depicted herein. First double-layer 12 and 14 or Hg(1−y)Cd(y)Te/Hg(1−x)Cd(x)Te (x<y) heterojunction (DLHJ) structure is grown by MBE (molecular beam epitaxy) or LPE (liquid-phase epitaxy) on CdZnTe or an alternate substrate 10 (FIG. 4a), where the upper HgCdTe layer is heavily doped p-type and the lower layer is lightly doped n-type. Then mesa diodes are reticulation by etching for forming trenches in the DLHJ structure as shown in (FIG. 4b), and a CdTe surface passivation layer 18 is deposited on the top and sidewall surfaces of the mesa structure by thermal evaporation in a vacuum deposition system shown in FIG. 3. In order for the passivation layer 18 to be effective, the CdTe/HgCdTe heterostructure is annealed at 250 C for several days in a system shown schematically in FIG. 1, where CdTe molecular beam is generated by heating CdTe solids in a Knudsen cell or a crucible and evaporate it into a CdTe flux comprising Cd, Te, and Te2 gas molecules, which condense on the HgCdTe substrate surface and form CdTe films. A flux monitor is used to measure the CdTe flux in real time. Additional beam sources can be inserted in the reaction chamber for co-deposition. FIG. 4c is schematic cross-section of the HgCdTe DLHJ mesas photodiode array 14 having trenches 16 for isolating the mesa photodiodes and CdTe layer 18 deposited on the sidewall of the trenches 16 for passivation. Finally, ohmic contact metal studs 8 are formed on each photodiode. FIG. 4d shows the cross-section of finished HgCdTe DLHJ photodiode array.
FIG. 5 shows the geometry of a planar HgCdTe heterojunction photodiode. It features a n-type HgCdTe layer 12 having low x-value (˜0.2) HgCdTe grown on CdTe substrate 10 with a CdTe passivation thin film 18 deposited on its top surface, a n-type HgCdTe layer 14 having high x-value (˜0.3), and small, localized arsenic-doped regions 20 in high x-value layer slightly spreading into the low x-value, n-type region 12 to the is formed in the HgCdTe to form a p-n junction whose boundary terminates at the top surface, which is passivated with a layer of CdTe and passivation annealing to avoid deleterious effects of excessive fixed charge and/or traps. An ohmic contact 8 is provided to make contact with the p-regions. Similar diode structure can be formed as homojunction photodiodes. This device structure does not require trenches but the p-n junction terminates at the top surface which must be passivated as well.
Newer generation DLHJ photodiodes have minimal diode area and very narrow trenches between them. The depth of the trenches cannot be scaled accordingly, however, giving rise to high aspect ratio trenches with steep sidewalls (FIG. 4e) that are difficult to coat completely with conventional vacuum deposited protective films. Additionally plasma etch processes with highly directional energetic ions used to etch the trenches invariably induced damages to the HgCdTe surface. The uses of these plasmas etch processes result in clean carbon and oxygen free surfaces with little Hg depletion. However, the moment they are removed from vacuum oxygen and hydrocarbon contamination start to build on the surface. An in-situ or minimally in-vacuo process to be developed that will chemically and electrically passivate high aspect ratio HgCdTe surfaces is needed. This passivation must be able to be vacuum compatible and not dope the HgCdTe it is passivating. More importantly, non-conventional methods such as atomic layer deposition (ALD), where mono-atomic layers of Cd and Te are deposited alternately, are needed to ensure good sidewall coverage even though the deposition rate of ALD process is very slow and must be performed at elevated temperatures of >250 C.
FIG. 6 depicts another HgCdTe photodiode architecture. The photodiodes are in form of vertical n-on-p homojunctions, they are called high density, vertically integrated photodiodes, or HDVIP because the p-n junction runs vertically from the top to the bottom surfaces. FIG. 6 shows schematic cross-section of photodiodes formed on a HgCdTe layer 20, which is adhesive bonded to ROIC (Readout IC) 10 with a thin epoxy layer 18, wherein localized n-type regions 12 are formed in the 10-um thick p-type HgCdTe layer, which is doped with the Group IIB vacancies and Copper. The HgCdTe layer with both front and back surfaces passivated with CdTe layers 18 using the DSID (double sided interdiffusion) process as described in U.S. Pat. No. 5,846,850. The HDVIP photodiodes are formed by using reactive ion etch (RIE) to form via holes 6 through the p-type HgCdTe layer. The energetic ions in the RIE removes Te and Cd during the etch from the via holes to free up Hg atoms, allowing them to diffuse interstitially in the HgCdTe matrix to annihilate the vacancies, displace and replace the copper impurity dopants to convert HgCdTe regions 12, which is within a few microns around the vias, from p-type to n-type, by lowering the p-type doping concentration to below that of indium, which is an n-type dopant, originally introduced into the HgCdTe, at a level of ˜5E14 cm-2. Metal layer 8 was deposited on the side and bottom of the via holes to form contact/metal interconnections between the photodiodes and the landing pads 22 in the ROIC 10. It should be noted that as described in U.S. Pat. No. 5,846,850, the HgCdTe was thinned to 10 um before both of its top and bottom surfaces were passivated with CdTe and interdiffusion annealed; the process is cumbersome as it require the thinned HgCdTe to be mounted on CTE-matched CdZnTe substrates temporarily with heat resistant epoxy for thinning and passivation anneal operations. The CdZnTe substrate must be removed from the HgCdTe after the stack is epoxy bonded to ROIC.
It can be seen that essentially all of the prior art HgCdTe anneal methods suggested using seal quartz ampoules to contain the Hg- or Cd-vapors needed. However, quartz ampoules are limited in size and for one-time use only; they cannot accommodate 6″ or larger wafers or be reused. In theory, Cd, which is in the same group as Hg in the Periodic Table, can be used for to replace Hg in annealing HgCdTe as an alternative to the Hg-rich anneal. In practice, however, it is difficult to use Cd in sealed ampoules. The main reason is the vapor pressure of Cd being too low. For instance, the vapor pressure of Cd at a common anneal temperature of 250 C is less than 1E-5 atm, in contrast to 0.1 atm of the commonly used Hg. Such a low vapor pressure was difficult to apply or control accurately or reproducibly and was not expected to keep metal vacancies from being generated from losing Hg to vaporizing from HgCdTe. Adding Hg to the Cd is not practical either, because Hg can act as a sink for Cd, and its overwhelming pressure diminishes Cd's presence to trace amount, which is difficult to control or adjust for the proper value of anneal.